Market — Advanced Packaging (CoWoS & SoIC)

Verified claims and product-axis read for Advanced Packaging (CoWoS & SoIC). Every fact below is sourced; every product judgment traces back to underlying signals.

Verified facts

• SK Hynix's HBM order book is reportedly sold out through 2025 and largely committed through 2026. ↗ (other)
• Amkor's Q4 2024 advanced SiP packaging revenue rose ~24% YoY driven by Apple A18/M-series content gains. ↗ (financial)
• ASE acquired Infineon's facility (USG / SPIL?) and continues consolidating capacity to ramp advanced packaging output by ~40% YoY in 2025. _(historical_event)_
• Amkor's R&D spending was approximately $215M in 2024 (~3.4% of revenue), heavily weighted toward advanced packaging. ↗ (financial)
• SK Hynix HBM3e 12-Hi began mass production in September 2024, ahead of Samsung's first 12-Hi mass production target. ↗ (other)
• TSMC has reportedly raised CoWoS prices by ~15-20% for 2025 contracts in response to demand outstripping capacity. ↗ (other)
• SK Hynix and TSMC announced a joint HBM4 collaboration in April 2024 where TSMC fabs the HBM4 base die using N5/N12 logic process. ↗ _(historical_event)_
• TSMC Arizona Fab 2 (N3) is scheduled for production start in 2028 but no CoWoS capacity is co-located, requiring shipment back to Taiwan for packaging until Amkor Peoria opens. ↗ _(historical_event)_
• NVIDIA B200 uses 8 HBM3e stacks at 192GB total memory and ~8TB/s bandwidth, requiring 2.5x reticle CoWoS-L interposer. ↗ _(technical_spec)_
• AMD MI300X uses 8 HBM3 stacks at 192GB total with TSMC SoIC for compute-on-I/O 3D stacking. ↗ (other)

Cross-cutting opportunities (industry read)

• PCIe Gen5/Gen6 & CXL Retimer / Switch IC — Hyperscale AI racks need PCIe Gen5→Gen6 + CXL retimers/switches just to keep host-to-accelerator links alive at scale; this is Astera Labs' core ALAB-listed business.
• 800G / 1.6T Co-Packaged Optics & Silicon Photonics module — Scale-out beyond ~100K GPU clusters (verified Colossus class) is bandwidth-bound; pluggable optics are hitting reach/power limits, so the industry is racing to ship CPO at 800G→1.6T while still selling AEC for short reach.
• UALink AI Scale-Up Fabric (GPU-to-GPU) — NVLink lock-in is the single biggest non-NVIDIA accelerator pain point; the UALink consortium is the answer and Astera is the first merchant silicon making it ship-worthy.

See the Products and Strategy modules for the full product list and forward-looking judgment.