Advanced-packaging integration engineer; CoWoS / SoIC / FOCoS-Bridge.

Audience Profile

• Age / Experience: 10-20 years experience, mid-career to senior
• Current role: Advanced Packaging Engineer / 2.5D-3D IC Integration (TSMC / ASE / Amkor / chip designer)
• Top pain points:
• Yield-loss attribution across substrate + interposer + die
• Capacity allocation politics across hyperscaler customers
• Bridge / RDL alternatives roadmap visibility
• Top decision blockers:
• IP licensing on advanced bonder + redistribution layer process
• Capex commitments for next-gen interposer line
• (Only 2 declared in source)

What This Segment Needs

• Information: Module-level roadmap visibility (CoWoS-L/-S, SoIC hybrid-bonding, FOCoS-Bridge cadence) and hyperscaler allocation reality vs marketing.
• Tools: TSV-etch / Cu-Cu bonding process libraries, FEA warpage models for 8-Hi/12-Hi stacks, KGSD test flows, ATE coverage for HBM3E/HBM4.
• Services: IP-licensing diligence on bonders + RDL; capex-risk modeling for next-gen interposer lines; reticle-size > 2x roadmap intel.

Top 5 Companies for You (Fit Score)

| Rank | Company | Score | Why | |------|---------|-------|-----| | 1 | TSMC | 84/100 | CoWoS doubling to ~75k wpm by end-2025, ~2x again 2026; NVIDIA Rubin R100 on N3P/CoWoS-L (Sep 2025) and Micron HBM4 base die (Apr 2025) locked. Five Feb-May 2026 senior reqs span TSV etch, CoWoS-L, SoIC hybrid bonding, HBM4 test. | | 2 | SK Hynix | 82/100 | World-first HBM4 dev completed Sep 26 2025; HBM3E 12-high shipping to NVIDIA since Mar 2025. 20T KRW M15X Cheongju operational Nov 2025. April 2025 TSMC MoU on HBM4 base die exposes DRAM engineers to N3 logic flow. | | 3 | Micron | 79/100 | HBM annualized run-rate >$8B (Sep 23 2025), data-center +100% YoY. HBM3E 12-high 36GB qualified on NVIDIA GB300. Principal HBM Packaging/TSV req (Feb 27 2026) maps 1:1 to your TSV + thermocompression + KGD pain points. | | 4 | ASE | 78/100 | US$1.6B 2025 capex at Kaohsiung K28 for FOCoS-Bridge + 2.5D/3D; AI ATM guided ~10% in 2026 (>2x 2024). VIPack supports >2x reticle interposers + 8-12 HBM3E/HBM4 stacks. NVIDIA Blackwell partner at GTC 2025. | | 5 | Samsung | 75/100 | HBM3E 12-high NVIDIA qual passed Sep 4 2025, Q4 2025 shipment start. Pyeongtaek P4 Phase 2 ~20T KRW for HBM4 in 2026. HBM4 base die on 4nm Samsung Foundry — cross-domain foundry+memory exposure not available at SK Hynix. |

Deal-Breakers (Your Hard Preferences)

No hard preferences declared for this segment.

How to Evaluate Any Company in this Niche (Checklist)

• [ ] Check growth signals: count senior reqs (Principal/Staff) tagged with specific process (CoWoS-L, SoIC, TCB, KGSD, hybrid bonding) posted in last 90 days — fewer than 3 distinct specialties = stalled roadmap.
• [ ] Check comp data: pull Levels.fyi + Blind for Hsinchu/Icheon/Boise/Kaohsiung packaging bands; flag if base + RSU is >25% below TSMC Principal CoWoS HBM Integration benchmark.
• [ ] Check learning signals: confirm at least one public HBM4 or 16-Hi TSV req on N3/4nm-class base die; absence = locked at HBM3E generation.
• [ ] Check stability signals: watch for CFO turnover during capex ramp (Micron had 2 in 12 months) and capex-vs-disclosed-customer gap (ASE K28 named only NVIDIA).
• [ ] Check culture signals: ask hiring manager which module owns yield-loss attribution across substrate/interposer/die — vague answer = political org.
• [ ] Check IP signals: ask which bonder + RDL processes are licensed-in vs internally developed; pure licensee = capped career ceiling on next-gen interposer.
• [ ] Check capacity politics: ask what % of allocation goes to top-1 hyperscaler customer; >50% = your roadmap is their roadmap.

Reverse-Hype Watch

• SK Hynix Q2 2025 41% OP margin is cyclical-peak; same ops posted 2023 losses — current trajectory not durable through a 2026-2027 AI capex pause.
• ASE K28 US$1.6B capex named only NVIDIA Blackwell as customer (GTC 2025) — capex pre-commitment outpaces disclosed customer signals; single-architecture miss hits utilization directly.
• Samsung HBM4 12-high March 2026 'sample shipments…positioning for NVIDIA/AMD qualification' repeats the exact HBM3E 12-high messaging pattern that slipped in Q2 2025.

Under-reported for this segment: cross-vendor yield-loss attribution practice — public coverage treats substrate, interposer, and die yields as separate stories, but the actual 2.5D/3D escape rate (and who eats it commercially when CoWoS-L warpage shows up at KGSD test) is almost never disclosed. Ask in the loop how disputed-failure cost is split between OSAT, memory vendor, and foundry; the answer reveals the real power structure.