HBM (High-Bandwidth Memory) Market Analysis — May 2026

Market Size & Growth

• **Current market size (USD):** ~$36–40B in CY2025, inferred from Micron's HBM annualized run-rate of >$8B at FQ4 2025 against its ~22% target share (signal `cd13dd7e`, `f2a8cb6d`). SK Hynix HBM contributed >40% of DRAM revenue in Q3 2025 on group revenue of 24.4T KRW (signal `6c2b52c8`).
• **3-year CAGR (2023→2026E):** ~65–75%. HBM was a ~$4B niche in 2023; the OpenAI Stargate LOI alone commits Samsung + SK Hynix to up to **900,000 DRAM wafers/month** combined (signal `168ed0d0`), and TSMC has guided CoWoS to roughly double again in 2026 after already doubling to **~75,000 wpm by end-2025** (signals `fc8c5297`, `f9208998`).
• **Key drivers:**
• HBM3E 12-high (36GB) ramp on NVIDIA Blackwell Ultra (B300/GB300) — all three memory vendors now qualified (signals `b67476b0`, `e3964fcf`, `f2a8cb6d`).
• HBM4 transition into 2026: SK Hynix completed world-first HBM4 development Sept 2025 (signal `fe64f30f`); Micron sampled June 2025 (signal `824b304a`); Samsung sampled March 2026 (signal `f01d75dc`).
• NVIDIA Rubin (R100) locked to **CoWoS-L + 8-site HBM4** on TSMC N3P, volume ramp 2026 (signal `d6da49ee`).
• Hyperscaler-direct contracting via OpenAI Stargate (signal `168ed0d0`).

Supply Chain

• **Upstream:** DRAM wafer fabs (SK Hynix M15X Cheongju, Samsung Pyeongtaek P4, Micron Idaho/NY) → TSV/MR-MUF stack assembly → advanced-node **logic base die** (TSMC N3/N5 for SK Hynix & Micron; Samsung Foundry 4nm in-house for Samsung HBM4).
• **Midstream (constraint):** **2.5D/3D advanced packaging** — TSMC CoWoS-S/-L (the binding capacity number), ASE VIPack/FOCoS-Bridge as merchant alternative, Amkor 2.5D in Arizona via TSMC partnership.
• **Downstream:** AI accelerators (NVIDIA Hopper/Blackwell/Rubin, AMD MI300/MI350/MI400, Intel Gaudi, AWS Trainium, Broadcom/Marvell ASICs) → hyperscaler training clusters (Microsoft, Meta, Google, OpenAI Stargate, xAI).

`[SK Hynix/Samsung/Micron HBM stack + TSMC base die] → [TSMC CoWoS-L / ASE FOCoS-Bridge / Amkor 2.5D] → [NVIDIA Rubin, AMD MI400, hyperscaler ASICs] → [Stargate-class clusters]`

Trend Lines (3 trends, ranked by importance)

**1. The HBM base die has become an advanced-logic problem, not a memory problem.**

• **Evidence:** "SK Hynix expanded its partnership with TSMC in April 2025 to co-develop HBM4 using TSMC's 3nm logic process for the base die" (signal `910ed7ff`). Samsung's March 2026 HBM4 sample uses a "**4nm logic base die from Samsung Foundry**" (signal `f01d75dc`).
• **Why now:** HBM4's >2 TB/s per-stack bandwidth and 2048-bit interface force the base die onto an N3/N4-class logic process — that wasn't true for HBM3, where mature memory nodes sufficed. The 2025–2026 capability shift is that HBM is now co-designed with the foundry's leading-edge logic PDK, which structurally couples Samsung Memory ↔ Samsung Foundry and SK Hynix/Micron ↔ TSMC.
• **Implication:** Over the next 6–12 months, HBM4 qualification timing on NVIDIA Rubin will be gated as much by foundry yield on the base die as by memory stack yield. Samsung's in-house lever is a genuine differentiator if it qualifies — and an industrial-policy weapon if it doesn't.

**2. CoWoS is the actual bottleneck. HBM cells are not.**

• **Evidence:** "TSMC reiterated plans to roughly double CoWoS advanced-packaging capacity to about 75,000 wafers per month by end-2025… 2025 capex of $38–42 billion" (signal `fc8c5297`); 2026 guide is another ~2x (signal `f9208998`).
• **Why now:** HBM4 stacks demand **>2x reticle-size interposers** and 8-site HBM placement around an >800 mm² compute die — only CoWoS-L (volume 2025) and ASE FOCoS-Bridge (ramping K28, $1.6B 2025 capex, signal `be39886f`) can do it. This is a 2025-specific capability that did not exist at volume in 2023.
• **Implication:** Through CY2026, accelerator-vendor allocation will be set by interposer wafers, not HBM stacks. Expect ASE's AI-mix guide of ~10% of ATM in 2026 (signal `9fec9da9`) and Amkor's Arizona buildout (signal `dee74ab0`) to act as the relief valve — and to compress the merchant-OSAT/foundry spread that NVIDIA currently pays.

**3. Hyperscalers are now contracting memory directly, ahead of the accelerator OEM.**

• **Evidence:** "Samsung Electronics signed a letter of intent with OpenAI to supply HBM and advanced DRAM for the Stargate AI infrastructure buildout, part of a combined Korean memory commitment of up to **900,000 wafers per month** with SK Hynix" (signal `168ed0d0`).
• **Why now:** Before 2025, HBM was sold into NVIDIA/AMD/Intel and tied to their forecasts. Stargate's October 2025 LOI is the first publicly disclosed hyperscaler-direct multi-year wafer commitment — only possible because hyperscaler capex envelopes (>$100B annual run-rate in 2026) now exceed accelerator-OEM working-capital tolerance for memory pre-buys.
• **Implication:** Memory OEMs gain a demand floor independent of NVIDIA's qualification cadence. Watch for a Microsoft, Meta, or Google equivalent LOI in 2026; that flips HBM pricing power away from accelerator vendors and toward the memory triumvirate.

Key Inflection Points (Watch List)

1. **NVIDIA HBM4 qualification on Samsung** — Samsung's March 2026 HBM4 sample (signal `f01d75dc`) targets 2H 2026 volume; pass/slip is the binary event for Samsung's competitive position vs SK Hynix.
2. **TSMC CoWoS exit-2026 run-rate** — guidance is ~150k wpm; any miss propagates immediately to NVIDIA Rubin and AMD MI400 ramps.
3. **SK Hynix M15X Cheongju ramp** — 20 trillion KRW HBM-dedicated fab started Nov 2025 (signal `9516af7d`); steady-state yields drive 2026 HBM share.
4. **Amkor Peoria first production (2027)** with $407M CHIPS Act funding (signal `dee74ab0`) — first US-sourced CoWoS-class back-end going live.
5. **A second hyperscaler-direct LOI** following OpenAI Stargate. The presence or absence of one through CY2026 determines whether the Stargate deal is a structural shift or a one-off.

Reverse-Hype Warnings

The dominant narrative — "**HBM is the AI bottleneck**" — is half-true and increasingly misleading. SK Hynix and Samsung have committed enough fab capex (20T KRW each at M15X and P4 Phase 2; signals `9516af7d`, `277e6a9e`) that by late 2026 the binding constraint will not be DRAM cells or TSV stacks — it will be **TSMC CoWoS-L interposers and the small set of OSAT lines that can co-package 8–12 HBM stacks around a reticle-plus logic die**. Industry commentary that conflates "HBM shortage" with "memory shortage" hides the real chokepoint, which is advanced packaging. Underrated, accordingly: ASE's $1.6B K28 buildout and Amkor's TSMC-partnered Arizona campus — both are pricing-power relief valves that the consensus is mis-modeling as marginal OSAT capex.

Also overhyped: **Samsung's 4nm in-house HBM4 base die as a guaranteed advantage**. The March 2026 announcement reads exactly like the 2024 HBM3E 12-high "positioning for NVIDIA qualification" language that ultimately slipped 3+ quarters and cost ~55% YoY operating profit (signal `4207bc06`). Until Samsung confirms NVIDIA HBM4 qual — not sample shipment — the 4nm differentiation is a promise, not a delivered customer outcome. Underrated, conversely: Micron's quiet execution. A $8B HBM run-rate and qualified Blackwell-Ultra volume from a #3 entrant with ~22% share (signals `cd13dd7e`, `f2a8cb6d`) is the cleanest "caught up faster than expected" story in the stack — and it sits on TSMC base die, meaning Micron benefits from the same logic-node leverage as SK Hynix without Samsung's foundry-coupling risk.