HBM Memory Hiring Signals — May 2026

Volume & Trend

• Total open roles (last 90d): 30 (vs previous 90d: 0; delta_pct unavailable — no prior-period baseline in dataset, so this is a cold-start cohort rather than a measured acceleration)
• Distribution by level: all 30 roles tagged level=unspecified. Free-text titles in the JD sample run heavy on "Principal" (5+), "Staff" (4+), and two "Director" slots (Samsung HBM Product Planning, Micron HBM Product Marketing) — seniority skews senior but the structured field is empty.

Top 5 Specialties (last 90d)

1. advanced packaging: 5 jobs at 5 companies
2. memory test: 4 jobs at 4 companies
3. DRAM circuit design: 3 jobs at 3 companies
4. TSV integration: 3 jobs at 3 companies
5. signal integrity: 3 jobs at 3 companies

Top 5 Hiring Companies (last 90d)

| Company | New Roles | Top Specialty | Avg Level | |---------|-----------|---------------|-----------| | SK Hynix | 0 | n/a | unspecified | | Samsung Electronics | 0 | n/a | unspecified | | Micron Technology | 0 | n/a | unspecified | | TSMC | 0 | n/a | unspecified | | ASE Technology | 0 | n/a | unspecified |

(Stats layer reports new_roles=0 across every company while total_roles_90d=30 — the company-level counter did not back-fill. The 20-row JD sample below remains the ground truth for who is actually posting; ASE Technology in particular has no JDs in the sample despite appearing in the top-5 table.)

Business-Talent Correlation Insights (3 most striking)

No correlation_links were supplied in this run (correlation_links: []). Per the constraint that every numeric must come from stats or correlation_links, this section is intentionally left empty rather than fabricated. Re-run after the business_signal ↔ talent_signal join is populated; the four leading-indicator clusters below are the candidate pairs to validate against.

Hiring as Leading Indicator

• SK Hynix: 5 HBM4 / advanced-packaging roles posted in the May 2026 window — Principal DRAM Design (2048-bit, >1.6 TB/s), Senior TSV at Icheon M16 for 16-Hi stacks, Staff Signal Integrity at 12.8 Gbps/pin, Hybrid Bonding Equipment Engineer at Cheongju, Senior KGS Test on Advantest V93000 — no public Cheongju Cu-Cu hybrid-bonding ramp disclosure yet; expect Q3 2026 announcement of a post-HBM4 stacked-memory pilot line.
• Samsung Electronics: 5 HBM roles concentrated at Hwaseong R&D and Pyeongtaek Line 4, including a Mid-Level 1c-nm DRAM integration role explicitly scoped to EUV layers for HBM die — no public 1c-nm HBM qualification has been confirmed; expect Q3-Q4 2026 customer-qual announcement tied to NVIDIA/AMD accelerator slots.
• Micron Technology: 5 HBM roles spanning Boise and Taichung, including a Principal Engineer hire that names "HBM4E" in scope alongside HBM4 — no HBM4E SKU has been publicly disclosed; expect Q4 2026 roadmap update formally naming HBM4E as a product line rather than an internal codename.
• TSMC: 5 advanced-packaging roles covering CoWoS-L/CoWoS-S for HBM3E/HBM4, SoIC Cu-Cu hybrid bonding for HBM4 base die at Hsinchu, TSV etch/fill for interposer + base die, FEA warpage analysis on 8-Hi/12-Hi stacks, and 2.5D KGS test — no public CoWoS-L allocation confirmation for HBM4 customers; expect Q3 2026 capacity guidance naming the HBM4 customer set.

Reverse-Hype Warnings

**JD over-marketing detected:** Almost none — and that itself is the signal. A keyword pass across the 20-JD sample for "rockstar", "world-class", "moonshot", "ninja", "guru", "10x" returns zero hits. The most aggressive phrasing in the entire corpus is "next-generation" and "leading AI accelerator customers". HBM hiring in May 2026 is being run by memory-fab HR organizations that gate candidates on JEDEC HBM compliance, ATE platform familiarity (Advantest V93000, T5503), and named tools (HFSS, ADS, CMP, thermocompression bonding) — not on cultural-fit theatrics. The hyperscaler-style JD inflation that dominates LLM and AI-agent roles has not penetrated this cohort, which suggests the HBM labor market clears on credentialed scarcity rather than on narrative.

**What's UNDER-reported:** Four conspicuous gaps in the sample. (1) Memory controller and PHY firmware — zero software-side roles, despite every HBM4 stack requiring a co-designed controller; controller headcount is presumably sitting at the customer (NVIDIA, AMD, hyperscaler-ASIC) rather than at the memory vendor, which means the supply-chain bottleneck is silently shifting toward GPU vendors' RTL teams. (2) System-level power and thermal architecture above the package — only one TSMC thermal-mechanical role appears, and no rack-power or cold-plate engineers, even though 16-Hi HBM4 at >1.6 TB/s materially changes accelerator board TDP. (3) LPDDR and standard DDR DRAM hiring is entirely absent from this slice — HBM appears to be cannibalizing memory-vendor headcount allocation, which has downstream implications for mobile and client DRAM roadmaps. (4) EUV mask, reticle, and pellicle engineering — Samsung's 1c-nm + EUV scope is buried inside a single mid-level integration JD; there are no dedicated EUV reticle roles, suggesting the real EUV-supply bottleneck is hidden inside generalist integration headcount rather than surfaced as standalone specialty hiring.