Market — CXL Memory Fabric

Verified claims and product-axis read for CXL Memory Fabric. Every fact below is sourced; every product judgment traces back to underlying signals.

Verified facts

• Marvell licensed CXL controller IP from a third party before in-housing Structera development per 2023 industry reporting. ↗ (other)
• Alphawave Semi's PCIe Gen6 / CXL 3.x SerDes IP was first taped out in 2024 on a 3nm node. ↗ _(historical_event)_
• Astera Labs' R&D headcount in CXL/memory connectivity grew from ~50 in 2022 to ~150+ by end of 2024 per LinkedIn signal. ↗ _(historical_event)_
• Liqid and MemVerge ship CXL-based composable memory software stacks that target Astera Leo and Samsung CMM hardware as supported targets. ↗ (other)
• Samsung announced in early 2024 that its CXL memory module passed Red Hat Enterprise Linux 9.3 hardware certification. ↗ _(historical_event)_
• Micron's prepared CXL revenue guidance has been absent from FY2024 and FY2025 earnings transcripts — HBM dominates the data-center memory narrative. ↗ (financial)
• Samsung's Scalable Memory Development Kit (SMDK) is open-source software for CXL memory tiering, released in 2022. ↗ _(historical_event)_
• Astera Labs' COSMOS software suite manages Leo CXL controllers in production and is the disclosed reason Meta selected Leo for an internal program. ↗ (other)
• Marvell's Structera X memory controller is fabricated on TSMC N5 process per Marvell's 2024 product brief. ↗ (other)
• Marvell signed multi-year HBM custom-chiplet agreements with Micron, Samsung, and SK hynix in December 2024, which include CXL co-development clauses for some SKUs. ↗ (other)

Cross-cutting opportunities (industry read)

• PCIe Gen5/Gen6 & CXL Retimer / Switch IC — Hyperscale AI racks need PCIe Gen5→Gen6 + CXL retimers/switches just to keep host-to-accelerator links alive at scale; this is Astera Labs' core ALAB-listed business.
• 800G / 1.6T Co-Packaged Optics & Silicon Photonics module — Scale-out beyond ~100K GPU clusters (verified Colossus class) is bandwidth-bound; pluggable optics are hitting reach/power limits, so the industry is racing to ship CPO at 800G→1.6T while still selling AEC for short reach.
• UALink AI Scale-Up Fabric (GPU-to-GPU) — NVLink lock-in is the single biggest non-NVIDIA accelerator pain point; the UALink consortium is the answer and Astera is the first merchant silicon making it ship-worthy.

See the Products and Strategy modules for the full product list and forward-looking judgment.