Foundry Capacity — Market

Verified claims and product-axis read for Foundry Capacity. Every fact below is sourced; every product judgment traces back to underlying signals.

Verified facts

• Samsung Foundry is picking up overflow demand as TSMC's leading-edge capacity saturates. ↗ (other)
• Intel Foundry is courting AI-chip customers as a second source to TSMC. ↗ (other)
• Foundry allocation — who gets wafers and packaging slots — has become a primary determinant of who ships AI chips. ↗ (other)
• HBM4 memory is sold out through 2026 with a reported ~171% year-over-year price surge, compounding the foundry/packaging bottleneck. ↗ (other)
• Arm's CEO has called memory 'the toughest' constraint, ranking it alongside advanced packaging above raw wafer supply. ↗ (other)
• The binding AI-chip constraints in 2026 are advanced-node (N3→N2) + CoWoS + HBM4 — not raw N3 wafers alone. ↗ (other)
• TSMC's N3 process is sold out, with lead times exceeding 50 weeks and capacity booked 18-24 months out. ↗ _(technical_spec)_
• CoWoS advanced packaging is sold out through 2027 (52-78 week lead times); NVIDIA booked ~60% of 2026 output. ↗ _(technical_spec)_
• TSMC plans to roughly 3.5-4x CoWoS capacity to ~130k wafers/month by end-2026 versus end-2024. ↗ _(technical_spec)_
• The newest 2026 accelerators are migrating to N2 (e.g. AMD MI400 on 2nm), shifting the binding constraint forward from N3. ↗ _(technical_spec)_

See the Products and Strategy modules for the full product list and forward-looking judgment.