Market — EDA & Chip-Design IP

Verified claims and product-axis read for EDA & Chip-Design IP. Every fact below is sourced; every product judgment traces back to underlying signals.

Verified facts

• Synopsys HBM4 IP shipped first silicon samples in 2025 ahead of broader market readiness. ↗ _(historical_event)_
• Cadence and Synopsys both reported >40% of 2025 revenue from customers also using competitor's tools (multi-vendor flow). ↗ (financial)
• Annual EDA seat licenses for an advanced-node design team of 100 engineers exceeds $30M for full tool flow. ↗ (financial)
• Cadence and Synopsys both reported that AI accelerator customers contributed >30% of design-IP revenue in 2025. ↗ (financial)
• Arm China (Anmou Technology) operates as ~47% Arm-owned independent entity; revenue contributed approximately 20% of Arm group in FY25. ↗ (financial)
• Synopsys.ai VSO.ai verification space optimization customer deployments grew >5x in 2025. ↗ _(historical_event)_
• Synopsys-Ansys integration plan targets >$400M in run-rate cost synergies by year 3 per deal announcement. ↗ (financial)
• Arm Total Access licensing model adopted by >30 customers as of 2025, including most hyperscalers. ↗ (other)
• Verifying a single sub-3nm SoC requires >1M CPU cores cumulative compute hours per Cadence customer benchmark. ↗ (other)
• Synopsys 224G Ethernet PHY IP design wins included at least 4 named hyperscaler/networking-ASIC customers disclosed in 2025. ↗ _(historical_event)_

Cross-cutting opportunities (industry read)

• PCIe Gen5/Gen6 & CXL Retimer / Switch IC — Hyperscale AI racks need PCIe Gen5→Gen6 + CXL retimers/switches just to keep host-to-accelerator links alive at scale; this is Astera Labs' core ALAB-listed business.
• 800G / 1.6T Co-Packaged Optics & Silicon Photonics module — Scale-out beyond ~100K GPU clusters (verified Colossus class) is bandwidth-bound; pluggable optics are hitting reach/power limits, so the industry is racing to ship CPO at 800G→1.6T while still selling AEC for short reach.
• UALink AI Scale-Up Fabric (GPU-to-GPU) — NVLink lock-in is the single biggest non-NVIDIA accelerator pain point; the UALink consortium is the answer and Astera is the first merchant silicon making it ship-worthy.

See the Products and Strategy modules for the full product list and forward-looking judgment.