Where AI networking silicon is hiring (and where it's just talk)

For RTL, DV, physical design, and architecture engineers, the AI networking stack is moving fast enough that career bets matter. Here is the radar based on what is shipping, what is in standards, and where headcount is actually opening — verbatim from the last 90 days of fabric-axis activity. Treat this as career signal, not investment guidance.

The protocol shift is real, not theoretical

Ultra Ethernet Consortium 1.0 targets roughly 1 million endpoints (fact 250ce3d7), and ESUN extends Ethernet semantics into scale-up domains (fact 32413951). For protocol architects and DV engineers, that translates into a deep pipeline of work: lossless behavior, RoCEv2 transport, congestion control on commodity Ethernet. Community discussion is openly tracking an InfiniBand → Ultra Ethernet transition.

Three incumbents are committing PM and silicon headcount around UEC. What this means for resumes: experience in transport-layer state machines, credit/grant flow control, telemetry-driven congestion control, and end-to-end UVM environments for fabric protocols is becoming a scarce skill. If you have selective-retransmission or packet-spraying DV experience, that is a hiring signal that did not exist two years ago.

800G → 1.6T merchant switching: the real revenue is here

Broadcom Tomahawk 6 is the 102.4T anchor (fact e070c95f). Arista's $750M FY25 AI back-end (fact 9b6493fe) and Celestica's converging system designs confirm that 51.2T → 102.4T Ethernet is the de-facto AI back-end. This is not a thesis — hyperscaler design wins are already monetizing.

For physical design engineers, switch ASICs at 102.4T-class radix are punishing: package complexity, on-die SerDes density, thermal envelopes, and floor-planning around 200G/lane macros. Specific scarce skills: large-die hierarchical PD, advanced packaging (CoWoS-class), and timing closure across many high-speed SerDes corners. RTL engineers with shared-buffer / VOQ scheduler experience and congestion-control microarchitecture — where the lossless parity gap with InfiniBand still sits — are also in demand.

AEC: from thesis to product

Inside-rack copper is no longer speculative. AWS Trainium and NVIDIA rack-scale designs have productized 1.6Tbps AEC links (fact ba213d85), and Semtech reported >100% YoY datacenter growth (fact cb28d21e). Credo is the pure-play but carries ~80% revenue concentration on a single anchor customer (fact 169a5e0e) — an operating risk to factor into a career decision, not a market call.

For mixed-signal designers, AEC is one of the more concentrated hiring zones: equalization, retimer architectures, low-power PAM4, link training firmware, and channel modeling. Anyone with cable-channel SI/PI experience or AEC-class retimer tape-out history is rare. The open question — when sub-3m optics become cost-competitive — is real but not imminent on reported timelines.

Optical DSP & SerDes retimer silicon: the quiet bottleneck

The 1.6T pluggable transition runs through 200G-per-lane PAM4 DSP (fact ba213d85). Credo is actively hiring SerDes designers (fact 23be5595). This is the layer under everything else, and the talent pool is thin.

Scarce skills here: analog/mixed-signal SerDes IP design (data converters, CDR, FFE/DFE), DSP architecture for PAM4 equalization, low-power CMOS at advanced nodes, and DV for SerDes link-up sequences. The structural risk for the merchant DSP path is hyperscaler in-house SerDes (AWS and Google have stated intent). Engineers should weigh whether they want exposure to that disintermediation or to be part of it inside a hyperscaler silicon team.

NVIDIA Spectrum-X / MRC vs Ultra Ethernet

The community is explicitly comparing MRC against Ultra Ethernet (demand_query 21f9b813). NVIDIA's vertically integrated NIC + switch + protocol stack hosts the largest deployed AI clusters today, and they are countering UEC with custom MRC transport.

For architecture and verification engineers, this is two distinct ecosystems hiring in parallel — NVIDIA's vertically integrated path, and the merchant Ethernet camp standardizing through UEC. Skills transfer between them at the SerDes and PHY layer; protocol-layer work tends to be ecosystem-specific. A bet on either is reasonable; a bet on one being the only survivor is not yet supported by the evidence.

Cisco Silicon One: a non-merchant alternative

Cisco's FY25 AI orders came in around $2B, roughly 2× target (fact d4537830), and silicon hiring is ongoing (fact 5bb3849e). Silicon One is one of the few non-merchant answers to Tomahawk 6. The structural pressure is that hyperscalers prefer multi-source merchant silicon — so per-port economics matter every roadmap cycle.

If you are weighing offers, Cisco Silicon One is hiring at scale but competes against a customer preference for merchant parts. That is a real risk factor for the team's long-term roadmap, though the reported order book suggests sustained near-term commitment.

How to read this radar

• Real commitment (silicon + orders + hiring): Broadcom (Tomahawk 6), Arista (system), Credo (AEC + SerDes), Cisco (Silicon One), NVIDIA (Spectrum-X / MRC).
• Standards-backed but earlier: UEC 1.0 / ESUN protocol work — high upside for transport-layer architects and DV leads willing to live in a standards body for a year.
• Concentrated risk worth naming: Credo's single-customer concentration; merchant DSP exposure to hyperscaler in-house SerDes programs.

The hiring signal across the stack: SerDes designers, switch-ASIC physical design engineers, congestion-control architects, and protocol DV leads are the four roles where demand is most visibly outrunning supply. Verify locally — this is what the last 90 days of fabric-axis evidence supports, not a forecast.