Anchor Customers Sort the AI ASIC Field

The sorting mechanism this quarter: who has a signed anchor

For silicon design engineers reading career signals out of the AI-ASIC field, the most useful lens right now is not TOPS or HBM stacks — it's anchor customers. The companies with named, sized, paying workloads are the ones that will keep funding tapeouts, growing PD teams, and staffing post-silicon. The ones still pitching are the ones where the next round of layoffs is one missed milestone away. Here's how the field sorts in the current evidence.

AMD MI450 — the most-anchored non-Nvidia product on the board

MI450 is the only non-hyperscaler ASIC in our evidence with two named hyperscale customers attached to specific numbers: an OpenAI commitment sized at 6 GW and an Oracle line for 50K MI450 units, alongside a $5B revolver and a publicly disclosed roadmap (MI300 → MI325 → MI350 → MI430X → MI450). That combination — funded customer + funded balance sheet + multi-generation roadmap — is what underwrites a stable hiring plan across RTL, DV, PD, and packaging. If you are evaluating where the work is durable over the next 12–18 months on the merchant side, MI450 is the most concretely backed product in the dataset. Treat that as evidence, not as a recommendation.

Hyperscaler ASICs: Trainium, TPU, and the Anthropic-shaped workload

AWS Trainium is the most-cited custom hyperscaler ASIC in demand chatter, and the Anthropic relationship effectively guarantees an inference workload it has to absorb. That matters for engineers because it converts Trainium from a speculative platform into one with a captive consumer — meaning the Annapurna RTL/PD/DV roadmap has a funded reason to keep iterating Trainium2 and beyond. Most of the visible headcount sits inside AWS/Annapurna rather than in the broader listed companies; Marvell remains the locked-in design-services partner, which is where the externalized seats show up.

Google TPU continues to be the canonical 'ASIC beats GPU' reference in investor and retail discourse. Broadcom is the disclosed silicon partner monetizing the relationship. Product–market fit here is not in dispute; the public chatter is itself the trend signal. For physical-design and SerDes engineers tracking where hyperscaler ASIC work is being externalized, Broadcom and Marvell remain the two names that absorb the most overflow.

Groq — the pure-play that already taped out

Groq's hiring shape tells you where the company is in its lifecycle. The chip exists; the LPU is in market; the sovereign-AI anchor deal outside US hyperscalers is the demand wedge. What Groq is hiring for now skews toward compiler engineers and capital-markets/financing roles, not raw RTL. Read that as the company moving from 'design the silicon' to 'finance the buildout and make the software story portable'. For engineers, the practical implication is that the scarce-skill demand at Groq is MLIR/compiler depth and runtime work, not new architecture seats.

Cerebras — the only fully-stacked story in evidence

Cerebras is currently the only AI-ASIC company in our evidence checking all five buckets: capex commitments, a named anchor customer, US datacenter expansion, named inference products (>2,500 tok/s on Llama 4 Maverick is the cited number), and — importantly for this audience — an open ASIC Architect requisition. That last detail is the one career-radar signal worth flagging: Cerebras is still hiring at the architecture layer, which means the wafer-scale roadmap is being iterated rather than parked. Hot signal, but treat any forward sizing of the business cautiously — the evidence is qualitative.

The compiler moat is doing more sorting than the silicon

A recurring requirement across the dataset is MLIR-based ML compiler experience. This is the wedge that decides which AI-ASIC startup actually survives contact with customers: the portability of HF/PyTorch workloads onto custom silicon, not the silicon itself. The hiring concentration is at the inference pure-plays — Groq and Tenstorrent are the two names absorbing the compiler talent, which is consistent with the read that their commercial survival depends on software ergonomics, not another tapeout.

For RTL, DV, and PD engineers, the implication is indirect but real: when you evaluate an ASIC company's job posts, the ratio of compiler/runtime openings to silicon openings is a useful proxy for where the company thinks its risk lives. A pure-play with five compiler reqs and one DV req is telling you the silicon is considered done.

What the market is actually asking

Public questions in the last 90 days that are worth noting because they map directly to this readership: 'Will AI replace ASIC Verification Engineers?' and 'Will ASICs lead in AI inferencing?' Both surface in the chatter we track. The DV question is a perennial; the inferencing question is the one that determines whether the hiring tilt toward inference pure-plays continues. Neither has a settled answer in the evidence — we are reporting that they are being asked, not that they have been resolved.

Career radar: the sort

• Funded merchant ASIC with named anchor demand: AMD MI450 (OpenAI 6 GW, Oracle 50K).
• Funded hyperscaler ASIC with captive workload: Trainium (Anthropic), TPU (Google internal); externalized seats at Marvell and Broadcom.
• Inference pure-plays past tapeout, scaling commercial + compiler: Groq, Tenstorrent — scarce skill is MLIR/compiler, not RTL.
• Fully-stacked wafer-scale story still iterating architecture: Cerebras — ASIC Architect req is the tell.

When you read the next batch of ASIC press releases, sort them by which of these buckets they land in. Companies with no anchor, no captive workload, and no compiler hires are the ones whose roadmaps you should discount, regardless of TOPS-per-watt slides.