The Packaging Seam Is Where the Money Is Hiring

Three independent non-NVIDIA accelerator programs are now competing for the same scarce talent: senior advanced-packaging IC engineers working at the chiplet/HBM/SI-PI interface. If you're reading hiring signals to plan your next move, this is the most concentrated convergence in the slice right now.

Who's hiring at the seam

AMD's Instinct MI450, Rebellions' REBEL, and Cerebras' Wafer-Scale Engine all have senior packaging roles posted on top of full RTL/DV/PD stacks. Three different architectures — monolithic CDNA-class accelerator, chiplet inference ASIC, wafer-scale die — converging on the same bottleneck. That convergence is the read: packaging, not RTL, is the contested moat for accelerators trying to credibly stand opposite NVIDIA. The lay-developer frustration on Reddit that "GPU/TPU vendors don't commoditize their RAM" reflects what insiders already know — HBM stacking, interposer routing, and UCIe-class die-to-die are where the schedule risk lives.

For PD engineers, the scarce sub-specialties showing up across all three job ladders look like: 2.5D/3D floorplanning with HBM stacks, SI/PI signoff on silicon interposer and organic substrates, thermo-mechanical co-design for stacked die, and UCIe PHY integration. RTL openings are plentiful. Senior packaging IC is not.

Where real capital has actually landed

The career-radar question is which programs have committed money and customers, not just slides. From disclosed datapoints in the last quarter:

• AMD MI450 has the strongest customer attach in the merchant slice — OpenAI's reported ~6 GW commitment and Oracle's ~50K-unit order are the first multi-GW non-NVIDIA datacenter AI awards. Execution risk sits in advanced-node plus packaging cadence against the reported H2 2026 ramp. If you're choosing between MI450 and a pre-revenue startup, that ramp date is the one to track.
• Cerebras closed a $1.1B Series G with G42 as anchor, plus a US datacenter buildout, and reportedly flexed ~3k tok/s on gpt-oss day one. Hiring is heaviest at wafer-scale PD and SI/PI — the hardest physical layer in the slice. The structural risk is concentration on a single sovereign anchor.
• Groq raised ~$750M and also shipped gpt-oss on day one on its LPU. Hiring runs hot on RTL plus compiler — the deterministic, software-scheduled thesis means compiler engineers are roughly as scarce as silicon engineers there. The gap to watch is multi-tenant production deployment outside flagship demos.
• Hyperscaler ASICs (Google TPU, AWS Trainium) are the largest committed programs by disclosed revenue. Broadcom is the lead silicon partner on TPU; Marvell signed a five-year extension on Trainium and is reportedly being pulled into Google's two-chip TPU roadmap as a second source. For ASIC engineers at merchant suppliers, Marvell's second-source role across both major hyperscaler programs is the single most concrete career signal of the quarter.

The pattern: real money is concentrated at merchant suppliers serving hyperscalers, the OpenAI/Oracle MI450 attach, and two well-funded ASIC startups with anchor customers. Programs without disclosed anchor revenue or capex are not yet hiring at the same pace.

What this looks like by job function

• RTL design. Broad market — LPU, MI450, TPU, Trainium, and WSE all have RTL openings. Specialization in matrix/tensor units, on-chip networks for chiplet meshes, and HBM controllers is the differentiated track. Compiler-adjacent RTL (Groq-style software-scheduled pipelines) is a niche but well-capitalized one.
• Design verification. UVM at multi-chiplet scope is the rising ask. DV engineers who can verify die-to-die UCIe links and HBM controllers against post-silicon failure modes appear hard to find based on repeat postings.
• Physical design. Tightest market in the slice. Wafer-scale PD (Cerebras), 2.5D interposer PD (AMD, Rebellions), and hyperscaler-ASIC PD share a small talent pool. Compensation reportedly follows.
• Architecture. Hyperscaler-attached architects at Broadcom and Marvell, plus inference-ASIC startups like Groq, dominate visible openings. Architecture roles tied to a specific anchor customer contract tend to outlast funding cycles — worth weighing against earlier-stage equity.

Watch items over the next two quarters

• Whether Anthropic's training mix actually lands meaningfully on Trainium, or stays hedged on GPUs. This calibrates the real upside for Marvell- and Annapurna-side roles.
• MI450 advanced-node and packaging execution against the reported H2 2026 ramp window.
• Multi-tenant Groq deployments beyond flagship demos — the LPU thesis hinges on this transition.
• Any second wafer-scale anchor for Cerebras beyond G42. Concentration is the visible weakness.

None of this is investment guidance. It is a read on which programs have put capital and customers behind their roadmaps, and which sub-disciplines those programs are competing for. If your next move is a packaging seat, the evidence suggests you have more leverage in this cycle than the last.