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AI Networking

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NETWORK-SWITCH-ENG-01

Switching silicon engineer at chip vendor or hyperscaler making whitebox builds.

Audience

  • · 8-18
  • Current: Switch ASIC Engineer / Network Silicon Architect
  • Pain: Roadmap visibility 2-3 generations ahead is the moat
  • Pain: Software toolchain maturity (SONiC / FBOSS / vendor NOS)

Product Needs

(none)

Channels

(none)

Competitor Lens

(none)

Fit Score weights — adjust to your priorities

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Top 5 for this segment
  1. 1. Cisco63/100
  2. 2. Arista Networks63/100
  3. 3. Credo Technology59/100
  4. 4. Celestica58/100
  5. 5. Semtech56/100

Full Persona Brief

Switching silicon engineer at chip vendor or hyperscaler making whitebox builds.

Audience Profile

  • Age / Experience: 8-18 years experience; mid-to-senior IC.
  • Current role: Switch ASIC Engineer / Network Silicon Architect (Broadcom / Marvell / Cisco / hyperscaler).
  • Top pain points: Roadmap visibility 2-3 generations ahead is the moat; Software toolchain maturity (SONiC / FBOSS / vendor NOS); Telemetry + INT (in-band network telemetry) standardisation.
  • Top decision blockers: Manufacturing capacity at advanced node for switch silicon; Channel-vendor product cycle alignment.

What This Segment Needs

  • Information: Shipped-silicon evidence (radix, Tbps, SerDes lane rate) plus 2-3-generation roadmap and advanced-node wafer allocation visibility.
  • Tools: Access to real NOS/toolchain ownership (SONiC/FBOSS/vendor NOS), pre-silicon emulation, and SI/PI lab for 112G/224G channels.
  • Services: Levels.fyi/offer-benchmark for Principal/Staff Silicon bands; design-win durability and customer-concentration disclosure before joining.

Top 5 Companies for You (Fit Score)

| Rank | Company | Score | Why | |------|---------|-------|-----| | 1 | Cisco | 84/100 | Shipped Silicon One P200 / Cisco 8223 (51.2 Tbps, 64x800G) Oct 2025 with successor-pipeline reqs; ~$2B FY2025 AI orders, >$1.3B single Q1 FY2026 quarter. Frontier shipped silicon, active Principal/Staff IC ladder. | | 2 | Arista Networks | 84/100 | UEC steering member, UEC 1.0 spec released 2025-06-11; Etherlink co-design on Broadcom Tomahawk 6 (102.4 Tbps). Q3 FY2025 $2.31B (+27%); open 'ASIC Design Engineer, Switch Silicon' 800G/1.6T SerDes. | | 3 | Credo Technology | 79/100 | 1.6 Tbps (200G-per-lane) AEC in production ramp; Q1 FY2026 record $222.8M +274% YoY. Caution: FY2025 10-K shows one hyperscaler ~86% of revenue. | | 4 | Celestica | 77/100 | Tomahawk 6 102.4 Tbps, 800G/1.6T, 112G/224G PAM4 SI/PI work; FY2025 ~$12.2B (+26.4%), three 2025 raises. Caveat: EMS/ODM applied model, sole-source whitebox, thin margin. | | 5 | Semtech | 74/100 | CopperEdge ACC moved to volume production; data center >100% YoY, three record quarters. Caveat: ~$50.3M Q1 FY2026 DC sales — growth off a low base. |

Deal-Breakers (Your Hard Preferences)

No hard preferences declared for this segment.

How to Evaluate Any Company in this Niche (Checklist)

  • [ ] Check growth signals: require ≥3 consecutive beat-and-raise quarters AND a named AI/DC order run-rate (e.g. Cisco >$1.3B/quarter); discount sub-$100M low-base lines like Semtech ~$50.3M.
  • [ ] Check comp data: no comp supplied here — pull levels.fyi Principal/Staff Switch-ASIC bands for the target before negotiating.
  • [ ] Check learning signals: confirm reqs cite shipped silicon (P200 51.2T, Tomahawk 6 102.4T) and 224G/200G-per-lane SerDes, not roadmap slideware.
  • [ ] Check stability signals: read latest 10-K customer concentration; flag any single hyperscaler >50% (Credo discloses ~86%).
  • [ ] Check learning/toolchain: ask whether ICs own NOS code (SONiC/FBOSS vs vendor NOS) and how INT/streaming telemetry (gRPC, P4) is standardised.
  • [ ] Check stability/supply: ask about secured advanced-node (3nm/5nm) wafer allocation for the next switch ASIC and 2-3-generation roadmap visibility for ICs.

Reverse-Hype Watch

Aggregated warnings: (1) Semtech data-center growth is off a low base (~$50.3M Q1 FY2026) despite the ~100%+ YoY headline; (2) Credo earnings are tethered to ~86% single-hyperscaler concentration; (3) Celestica upside rides sole-source whitebox programs on Broadcom's Tomahawk 6 roadmap — one design loss or capex pause hits the org.

Under-reported for this segment: public coverage chases Tbps headlines and order numbers, but rarely the things that decide a switch-silicon career — secured advanced-node wafer allocation, durability of merchant-silicon design wins across the next 2-3 generations, and whether ICs actually own the software toolchain (SONiC/FBOSS/vendor NOS) versus inheriting a closed stack. None of the Top 5's culture scores are grounded in Glassdoor or employee testimony; treat tone as inferred and verify roadmap-visibility and toolchain ownership directly in interviews.