{"slug":"ai-asics","title":"AI ASICs","tagline":"Hyperscaler silicon: TPU, Trainium, MTIA, Maia — and the merchant gap they create.","hub_url":"/topic/ai-asics","counts":{"companies":10,"business_signals_90d":70,"talent_signals":372,"jobseeker_profiles":5,"fit_scores":0},"companies":[{"slug":"cerebras-systems","name":"Cerebras Systems","primary_layer":"L4","description":"Wafer-scale Engine — single-chip alternative to multi-chip GPU clusters. Filed for IPO in 2024 (deferred). Real production deployments in scientific / pharma + select hyperscaler inference.","profile_url":"/companies/cerebras-systems"},{"slug":"sambanova-systems","name":"SambaNova Systems","primary_layer":"L4","description":"Reconfigurable Dataflow Architecture (RDU) — appliance + cloud model. Strong enterprise + government deployments. Pivoted toward inference-of-large-models from training focus.","profile_url":"/companies/sambanova-systems"},{"slug":"tenstorrent","name":"Tenstorrent","primary_layer":"L4","description":"Wormhole + Blackhole AI chips on RISC-V cores. Open-source software stack (TT-Metalium). Jim Keller-led architecture; named in multiple sovereign-AI government compute initiatives.","profile_url":"/companies/tenstorrent"},{"slug":"rebellions-ai","name":"Rebellions","primary_layer":"L4","description":"Korean AI inference chip startup. Atom chip + REBEL roadmap. Merged with Sapeon (SK Telecom AI chip subsidiary) in 2024. Sovereign-Korea-AI angle on inference silicon.","profile_url":"/companies/rebellions-ai"},{"slug":"synopsys","name":"Synopsys","primary_layer":"L4","description":"EDA leader — synthesis, place-and-route, verification, and the largest commercial silicon IP portfolio.","profile_url":"/companies/synopsys"},{"slug":"alphawave-semi","name":"Alphawave Semi","primary_layer":"L4","description":"High-speed connectivity IP — SerDes, chiplets, and custom silicon for AI / datacenter interconnect.","profile_url":"/companies/alphawave-semi"},{"slug":"etched","name":"Etched","primary_layer":"L4","description":"Transformer-only inference ASIC (Sohu) — bets the whole die on the transformer architecture for far higher throughput-per-dollar.","profile_url":"/companies/etched"},{"slug":"cadence","name":"Cadence Design Systems","primary_layer":"L4","description":"EDA leader — digital + analog implementation, simulation, and verification tools spanning the chip-design flow.","profile_url":"/companies/cadence"},{"slug":"siemens-eda","name":"Siemens EDA","primary_layer":"L4","description":"EDA (ex-Mentor Graphics) — Questa/UVM verification, Tessent DFT, Calibre physical verification.","profile_url":"/companies/siemens-eda"},{"slug":"groq","name":"Groq","primary_layer":"L4","description":"LPU inference-only accelerator; deterministic-latency architecture. GroqCloud commercial inference service. Sample point for inference-specialised non-NVIDIA silicon path.","profile_url":"/companies/groq"}],"generated_at":"2026-07-05T09:08:30.479Z","personas":[{"segment_id":"AIASICS-EARLY-01","one_liner":"An early-career hardware or software engineer (0-3y) passionate about learning the intricacies of novel AI ASIC architectures and their software stacks to build foundational expertise in this rapidly evolving field.","url":"/topic/ai-asics/personas/AIASICS-EARLY-01"},{"segment_id":"AIASICS-SENIOR-01","one_liner":"A senior hardware or software engineer (3-10y) driven by the ambition to join a rapidly growing AI ASIC startup that is challenging NVIDIA's dominance and offers significant career advancement opportunities in a dynamic market.","url":"/topic/ai-asics/personas/AIASICS-SENIOR-01"},{"segment_id":"AIASICS-STAFF-01","one_liner":"A staff-level or lead engineer (10y+) in chip design, verification, or compiler development, prioritizing long-term project stability and the opportunity to apply deep expertise in established or well-funded AI ASIC initiatives, potentially in sovereign AI or large enterprise deployments.","url":"/topic/ai-asics/personas/AIASICS-STAFF-01"},{"segment_id":"AIASICS-RESEARCH-01","one_liner":"A research-oriented PhD holder with specialized expertise in AI accelerator architectures, compiler optimizations for novel hardware, or advanced packaging, seeking highly compensated roles that value deep, niche technical contributions in cutting-edge AI silicon R&D.","url":"/topic/ai-asics/personas/AIASICS-RESEARCH-01"},{"segment_id":"AIASICS-SENIOR-02","one_liner":"A senior engineer (3-10y) in AI hardware or software development, seeking a role within an AI ASIC company that fosters a strong, collaborative culture, values open-source contributions, or champions a unique, mission-driven approach to challenging the status quo in AI compute.","url":"/topic/ai-asics/personas/AIASICS-SENIOR-02"}]}